In the design of digital logic circuits, low power performance and size minimization are essential. With the development of metal-oxide-semiconductor (MOS) techniques, the realization of low power performance has been accomplished. Low power performance in digital logic MOS circuitry has been obtained through two approaches. A first approach has utilized a CMOS design. CMOS designs have essentially achieved zero static current drain, but suffer from an inherently large die area and large number of process steps. A second approach to achieve low power performance of digital logic MOS circuits is the use of a single channel "ratioless" design in which the logic circuit does not depend on a ratio of resistances as utilized in enhancement driver-depletion load inverters. As used and understood herein, ratioless design permits no DC paths to a ground potential in the logic circuit. Ratioless logic has been shown to offer the benefits of low power dissipation together with small device geometries to provide a smaller device layout and the simplicity of a single channel fabrication process.
Ratioless logic and single channel fabrication processes have been utilized in a number of ratioless logic configurations. One MOS large scale integration (LSI) circuit function is a digital delay line or shift register. MOS shift register design has proven valuable in that the high impedance of an MOS device gate permits temporary data storage in the form of charge in parasitic capacitance. MOS technology permits realization of bidirectional transmission with a zero voltage offset across the device and the load devices may be turned off, as desired, by multiple clocks to reduce power dissipation. MOS shift registers have additional advantages in having smaller chip sizes. MOS shift registers have found application in computer display terminals, electronic calculators and computer peripherals such as memory circuits. Such use is dynamic wherein clock logic is utilized such that inputs must be loaded at a particular time and outputs can be valid and received at predetermined time periods. The application of digital logic MOS circuitry implemented in dynamic shift registers is described in a publication entitled MOS/LSI Design and Application, written by William N. Carr and Jack P. Mize (Copyright 1972, McGraw-Hill Book Company) at pages 150-167 and a publication entitled MOS Integrated Circuits, edited by William M. Penney and Lillian Lau (Copyright 1972, Vann Nostrand Reinhold Company) at pages 260-288.
While ratioless logic and single channel fabrication processes have found extensive use in dynamic register applications, such use has been limited in the design of random logic circuitry. This limitation is principally seen from numerous problems associated with most ratioless logic design schemes. One deficiency in existing ratioless logic schemes is that charge sharing between the logic output capacitance and the input capacitance of a stage to be driven results in a reduced output logic level. This reduced output logic level decreases the noise margin of the device and renders low voltage operation difficult. Another disadvantage in previously developed ratioless logic is degraded logic levels, due not only to charge sharing but also due to gate-to-source and gate-to-drain overlap capacitances. Degraded logic levels occur due to undesirable coupling between clock signal lines and logic nodes. An additional disadvantage with previously developed ratioless logic circuits is that numerous different clock phases must be generated unless a two-phase clock approach is utilized. However, most two-phase clock approaches cannot be utilized with feedback loops having odd numbers of inverting stages. Such feedback loops are essential in constructing even the simplest random logic circuit such as a toggle flip-flop. Additionally, previously developed ratioless logic schemes suffer from the nonavailability of the full supply voltage from logic outputs due to threshold voltage losses even ignoring the previously mentioned deficiency caused by the effect of charge sharing. This disadvantage creates a problem for one logic block of a circuit to serve as a clock source for subsequent logic blocks. Finally, previously developed ratioless logic schemes suffer in that clock loading can become undesirably high due to large numbers of gates, drains and sources tied to clock lines.
A need has thus arisen for a ratioless dynamic logic device which offers the advantages heretofore present for ratioless logic, namely low power dissipation and small geometry devices while eliminating the problems heretofore present for random logic application. A need has arisen for a logic device in which the effect of charge sharing between logic output and input capacitances of a stage are minimized to maintain the full original logic level for voltage. A need has further arisen for a logic device in which odd numbers of inverting stages can be incorporated in feedback loops wherein a two-phase clock approach is utilized to simplify clock generation. A still further need has arisen for a logic circuit in which logic outputs gate full supply voltage clocks to minimize the use of multiple clock phase systems. Additionally, a need has arisen for a logic device in which clock loading permits the charge required for operation to be applied directly from a supply voltage rather than the clock phase itself.